As the design rule for integrated circuits is continuously scaled down, the dimension of damascene opening is continuously reduced. Therefore, the step coverage of a barrier layer covering the inner surface of the damascene opening is getting worse, and defects may be formed in the barrier layer. For example, if 30-50 Å of barrier layer is blanket deposited on a wafer, the thickness of the barrier layer on sidewalls of openings, including vias and trenches, may be less than 5-10 Å. Therefore, defects can be easily formed in the barrier layer located on sidewalls of openings.
Since barrier layer is used to surrounding the later formed metal interconnect to prevent metal from diffusing into the dielectric layer where the damascene opening is located, these defects in the barrier layer provide passages for the metal diffusion. Moreover, the low-k dielectric layer mostly made from porous dielectric materials make the problem of metal diffusion through defects in the barrier layer more serious, since the larger the total pore volume of the porous dielectric material has, the lower the dielectric constant of the porous dielectric material has.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the disclosure, are simplified for explanatory purposes, and are not drawn to scale.